FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing a design, placement of components on the FPGAs, and routing connections between components on the FPGA utilizing available resources can be the most challenging and time consuming. In order to satisfy placement and timing specifications, several iterations are often required to determine how components are to be placed on the target device and which routing resources to allocate to the components. The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. Automated placement and routing algorithms in EDA tools perform the time consuming task of placement and routing of components onto physical devices.
When modifications are made to a design of a system, current EDA tools require a re-work of the entire placement and routing procedures. This may require a significant amount of time. In situations when the modifications are minor, re-work of the entire placement and routing procedures is inefficient and undesirable and discourages designers from effectively carrying out the typical design flow which involves making small changes to a design and analyzing the effects of the changes.
Thus, what is needed is an efficient method and apparatus for performing incremental compilation on FPGAs.